Conventional nonvolatile semiconductor memories, such as flash electrically erasable programmable read only memories (Flash EEPROMs), typically comprise a floating gate memory cell, which includes a source region, a drain region and a channel region formed in a semiconductor substrate, and a floating gate formed above the substrate between the channel region and a control gate. One method of programming or erasing a floating gate memory cell, utilizing a phenomenon known as Fowler-Nordheim tunneling, comprises applying a voltage differential, such as about 16 volts to about 23 volts, to the control gate while the channel region is kept at a low voltage, such as about 0 volts to about 2 volts, to force electrons into the floating gate. This movement of electrons is referred to as programming, and the high voltage (i.e., about 16 to about 23 volts) applied to the control gate is known as program voltage. A similar method is employed to erase the memory cell by reversing the direction of bias to force the electrons out of the floating gate.
Flash memory systems conventionally comprise a two-dimensional array of floating gate memory cells. One such array architecture is called NAND architecture, which typically includes several strings, known as NAND strings, of floating gate memory transistors, each transistor coupled to the next transistor in the string by coupling the source of one device to the drain of the next device to form bit lines. A plurality of word lines, perpendicular to the NAND strings, each connect to the control gate of one memory cell of each NAND string.
To supply program voltage on demand to each of the word lines, a CMOS transistor referred to as a "row selector" is employed at one end of each word line. The drain junction of this rowselecting transistor must be able to handle voltages of about 20 volts or higher, typically under gated diode conditions (i.e., with gate grounded). Therefore, in order to attain an acceptable level of performance and reliability, it must exhibit high gated diode breakdown voltage characteristics to avoid junction breakdown. Conventional processing techniques require many separate photolithographic masking steps to manufacture this transistor. The large number of masking steps raises the production cost of the Flash memory device and increases the probability of defects in the finished device.
There exists a need for simplified methodology in manufacturing a high voltage, high performance transistor with fewer processing steps, thereby reducing manufacturing costs and increasing production throughput.